Although compile-time is a good excuse for leaning back a while I am mostly annoyed by it..
But what affects the compile the most? CPU (Cores/Speed)? Disk-speed?
Or is it just bottlenecked by old code that makes up the compiler?
Although compile-time is a good excuse for leaning back a while I am mostly annoyed by it..
But what affects the compile the most? CPU (Cores/Speed)? Disk-speed?
Or is it just bottlenecked by old code that makes up the compiler?
Hi Anders,
Maybe put this on the ideas portal. I suspect you'll get a few votes...
Plant SCADA | AVEVA Plant SCADA (aha.io)
In short, yes there is plenty of opportunities to modernize it. The best thing you can do is give it high clock speed.
Hi Anders,
Maybe put this on the ideas portal. I suspect you'll get a few votes...
Plant SCADA | AVEVA Plant SCADA (aha.io)
In short, yes there is plenty of opportunities to modernize it. The best thing you can do is give it high clock speed.
Maybe I should post it there, but if such a crucial part of using and developing in Citect hasn’t been upgraded in all this time, there must be a reason. I can’t be the first one rising this question.
But I thank for clarifying what I suspected, and throwing GHz at it goes hand in hand with it being based on old code.